Integrated circuit design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the process of designing an integrated circuit (IC). An electronic circuit design is evaluated using device models. Device models often are implemented as design cells that describe the circuit behavior and connectivity of circuit elements, logic gates, and circuit blocks that may be included within a design. More complex cells may represent macros or a collection of gates and storage elements that implement more complex functions. An IC design may include many instances of a given cell. A computer software based simulation tool uses these cell-based models and interconnections to simulate operation of a circuit represented by the design.
Timing and signal integrity (SI) are increasingly important issues in integrated circuit design, particularly due to drastic scaling down of layout geometries and increase in operating frequencies. Static Timing Analysis (STA) tools are used to analyze whether a design meets timing constraints and SI requirements. STA involves determining the expected timing of a digital circuit to verify that all signals will arrive neither too early nor too late, and hence that proper circuit operation can be assured. For example, STA can be used to establish whether all paths within a design meet stated timing criteria, that is, that data signals arrive at storage elements early enough for valid gating but not so early as to cause premature gating. STA typically aims to find worst-case delay of a circuit over all possible input combinations.
Typically, in order to prepare a cell for use with a STA tool, the cell is pre-characterized as a function of parameters such as slew and delay and output load, for example. Characterization of a cell results in a simplified model of the cell suitable for use in STA. In general, characterization of a cell typically involves analog simulation of the cell using a suitable analog model of the cell. During analog simulation, an analog simulator configures a computer system to determine the behavior of the cell in response to input signal conditions by solving an analog system matrix representative of Kirchhoff s Laws. Each circuit element represented in the analog model can have an instantaneous influence on any other circuit element represented in the model and vice versa. As such, analog simulation typically is more complex and requires matrix based computation of complex mathematical equations, and therefore, takes far more time than STA.
STA typically aims to find worst-case delay of a circuit over all possible input combinations. Delay variations result in variation in the maximum possible operating frequency of an IC. Delay of a gate cell depends upon input signal slew and capacitive output load of the gate. However, delay also depends upon current flowing through transistors during switching, while charging or discharging the load. The current that flows during charging and discharging may depend upon processing variations during manufacturing and also may depend upon other factors such as voltage supply variations and heat during operation of the IC, for example. In order to account for these variations, STA for a given design cell is performed multiple times to estimate delay at various ‘corners’ such as best case and worst case corners. In a best case corner, smallest delay is considered, which implies a low capacitance and fast transistors, high voltage and low temperature. Conversely, in a worst case corner, highest delay is considered, which implies high capacitance and slow transistors, low voltage and high temperature.
An implicit assumption is that all waveform shapes reaching the input of an instance of a cell in a design resemble the shapes used in device characterization and can be accurately described by one or more predetermined parameters used in the characterization. However, as IC designs feature sizes reach deep sub-micron dimensions such as with sub-45 nm technologies, for example, waveform shape variations occur that are not readily described by the parameters used in pre-characterization of a device model. Waveform shape effect (WSE) refers to shape variations that are in addition to any waveform shapes encoded in a cell characterization library during pre-characterization of the cell. Some causes of these waveform shape changes include: noise-induced changes in waveform shape, particularly non-monotonic waveforms; long waveform tails, particularly in base delay calculations, often arising from long resistive interconnect; and back-Miller corrections for a following stage. Thus, the voltage waveforms observed in modern ICs may differ significantly from the voltage waveform assumptions of STA tools and often do not correlate with the waveforms used for cell characterization. As a result, conventional static timing analysis tools often are unable to capture non-idealities in the waveforms such as, for example, overshoots, spikes, ringing, etc.
Additionally, it is often difficult to exhaustively pre-characterize the cells for all possible loading conditions. Thus, approximate equivalent capacitance models are formed to generate represent loading due to interconnects between design cells, for example. Due to these approximations and the intrinsic limitations of the cell-based models, the generated output waveforms often do not match the real circuit behavior. The problem is more severe in the case of non-linear loading conditions, such as when other gate cells are coupled to the output of a driver cell as fan-out gates. The problem can be even further exacerbated due to large changes in transistor and interconnects characteristic in the presence of process variations.
Equivalent waveform models (EWMs) have been proposed to predict WSE during STA. See, for example, commonly assigned U.S. patent application Ser. No. 12/960,387, entitled Equivalent Waveform Model for Static Timing Analysis of Integrated Circuits, by Igor Keller et al. An EWM is a waveform that is equivalent to a more complex waveform e.g., a waveform that has noise induced changes or distortions due to Miller effects. An EWM has a shape that is suitable to cause a circuit element to which the EWM is applied during STA, to produce an output waveform that is the same as or substantially similar to an output waveform expected to be produced if the more complex waveform was to be applied to the same circuit element.